| error_rate_rx_1b4l_test Project Status (06/24/2013 - 22:00:38) | |||
| Project File: | kc705_0b1248_test_v00.xise | Parser Errors: | No Errors |
| Module Name: | error_rate_rx_1b4l_test | Implementation State: | Translated |
| Target Device: | xc7k325t-2ffg900 |
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No Errors |
| Product Version: | ISE 14.5 |
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183 Warnings (0 new) |
| Design Goal: | Balanced |
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| Design Strategy: | Xilinx Default (unlocked) |
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| Environment: | System Settings |
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| Device Utilization Summary (estimated values) | [-] | |||
| Logic Utilization | Used | Available | Utilization | |
| Number of Slice Registers | 589 | 407600 | 0% | |
| Number of Slice LUTs | 937 | 203800 | 0% | |
| Number of fully used LUT-FF pairs | 523 | 1003 | 52% | |
| Number of bonded IOBs | 117 | 500 | 23% | |
| Number of BUFG/BUFGCTRL/BUFHCEs | 8 | 200 | 4% | |
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | 金 6 28 15:37:43 2013 | 0 | 182 Warnings (0 new) | 13 Infos (0 new) | |
| Translation Report | Current | 金 6 28 15:38:15 2013 | 0 | 1 Warning (0 new) | 0 | |
| Map Report | Out of Date | 金 6 28 15:37:13 2013 | 0 | 207 Warnings (0 new) | 7 Infos (0 new) | |
| Place and Route Report | Out of Date | 金 6 28 15:37:49 2013 | 0 | 8 Warnings (0 new) | 1 Info (0 new) | |
| Power Report | ||||||
| Post-PAR Static Timing Report | Out of Date | 金 6 28 15:37:42 2013 | 0 | 0 | 3 Infos (0 new) | |
| Bitgen Report | Current | 金 6 28 15:38:52 2013 | 0 | 5 Warnings (0 new) | 1 Info (0 new) | |
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| WebTalk Report | Out of Date | 金 6 28 15:36:35 2013 | |
| WebTalk Log File | Out of Date | 金 6 28 15:36:33 2013 | |